1. Field of the Invention
The present invention relates to a computer system. More particularly, the present invention relates to an instruction controller and interrupt control method that are used in an embedded system.
2. Description of the Related Art
In recent years, embedded systems have been used in every field in society, and have been taking important roles. Specifically, the embedded systems are used in a wide variety of fields such as digital cameras, mobile phones, DVD players, robots, flight control systems, fuel injection systems and automatic brake systems of automobiles.
A conventional general definition of an embedded system is a computer system including hardware and software combined in a tightly coordinated manner so as to execute a dedicated function.
Additionally, one of the features that an embedded system is required to have is a real-time performance capability. Specifically, the embedded system normally receives a notification as an interrupt from an input-output device in order to quickly respond to changes in conditions of the input/output device coupled to the embedded system. An interrupt signal is inputted to an interrupt controller, and then is enabled or suspended in accordance with a value set in an interrupt mask register upon the receipt of the interrupt signal. An enabled interrupt is looked up in an interrupt table, whereby control is shifted to an interrupt handler in a vector address corresponding to the enabled interrupt.
Here, interrupt processes are respectively assigned priority orders based on their urgency. If a higher priority interrupt process occurs during execution of a lower priority interrupt process, the control is passed to the higher priority interrupt process, and the lower priority interrupt process is suspended and waits until the higher priority interrupt process is completed. Then, after completion of the higher priority interrupt process, execution of the lower priority interrupt process restarts.
On the other hand, if a lower priority interrupt process occurs during execution of a higher priority interrupt process, the lower priority interrupt process cannot immediately start to execute, and goes into a suspended state to wait until the a higher priority interrupt process is completed. In general, interrupt processes based on such priority orders are executed in accordance with a value set in the above interrupt mask register.
Meanwhile, an ECU for an engine of an automobile, for example, has the following problem. Specifically, as an engine rotor rotates, interrupt processes for calculating a top dead center sequentially come into an ECU of an automobile engine. Then, interrupt processes for causing fuel injection and ignition come in after the completion of the processes for the top dead center calculation. The processes for the top dead center calculation need to be completed before the interrupt processes for causing fuel injection and ignition. Otherwise, the processes are required to be temporarily cancelled for the purpose of securing reliability. This is called run time constraints.
In order to be cancelled properly, the interrupt processes need to be appropriately assigned priority orders under the run time constraints. Inappropriate priority orders may cause another interrupt process to come in during execution of processes under the run time constraints, and thus make it more difficult to meet the run time constraints.
In the above example, the interrupt processes for the top dead center calculation can be executed with a higher priority order, whereas the interrupt process for the fuel injection and ignition can be executed with a lower priority order. Such settings prevent the interrupt processes for the fuel injection and ignition from starting until the interrupt processes for the top dead center calculation are completed. Thereby, the order of the processes is fixed. However, a lower priority interrupt process cannot be executed unless a value in the interrupt mask register is changed to a lower value.
According to a conventional method for achieving such execution, the execution of an interrupt process to be processed next with a lower priority order is enabled by executing an instruction to change the content of an interrupt mask register while calling the lower priority interrupt process through a usual call instruction. However, the method has a problem of sometimes allowing another interrupt process to come in between the call instruction and the instruction to change the content of the interrupt mask register, because of the incapability of masking such interrupt instruction.
According to another conventional method, when a process to be processed next with a lower priority order is called, a software interrupt is caused to execute an instruction to change content of an interrupt mask register. In this case, all other interrupt processes also come in together in the beginning of the next interrupt process. Consequently, the next interrupt process cannot be prevented from being influenced by another interrupt process.
To cope with this, another conventional method utilizes an interrupt from a peripheral device. Specifically, an instruction for changing content of an interrupt mask register is executed upon reception of an interrupt from a peripheral device. Such execution of the interrupt from the peripheral device can greatly prevent other interrupt processes from coming in during the execution, thus improving process reliability. However, the method has a problem that the execution takes a long time due to utilization of a peripheral device.
Japanese Patent Application Publication No. Hei. 10-074148 discloses a technique in which a priority judgment circuit selects an interrupt process from one or more interrupt requests that have occurred; a comparator compares a level signal indicating a priority level assigned to the selected interrupt process with a priority level outputted from an instruction abort resister to allow the abort of an instruction; and an abort signal and the request for the interrupt process are outputted to a central processing unit if the priority level assigned to the requested interrupt process is higher than the priority level to allow the abort of the instruction.
Japanese Patent Application Publication No. 2004-199558 discloses a technique of executing a low priority interrupt handler when a high priority interrupt handler goes into an event-waiting state during its execution in the following manner. Specifically, at that moment, a priority order controller changes the priority of the high priority interrupt handler to the lowest priority. In addition, an execution arbitrator saves the content of a register necessary to surely continue the processing of the high priority interrupt handler, in a register reserved area fixedly reserved in a stack area for the high priority interrupt handler. At the same time, the execution arbitrator loads the content in a register reserved area for the low priority interrupt handler, and thus causes the low priority interrupt handler to be executed.
Japanese Patent Application Publication No. 2007-128396 discloses a technique of: disabling occurrence of an interrupt event during execution of an interrupt handler called upon reception of the interrupt event; activating a start process task assigned a lower execution priority level than a normal application; activating a data processing task when an execution right is passed to the start process task; executing data processing related to an interrupt factor causing the interrupt event when the execution right is passed to the data processing task; and then enabling the interrupt event again.
Even these prior art documents, however, neither suggest nor disclose any technique which prevents influence from another interrupt while a value of an interrupt vector is changed. Without such a technique, numerous interrupt patterns may occur when control is passed from a higher priority interrupt process to a lower priority interrupt process. Designing a program whose proper operation is guaranteed for all of the interrupt patterns is difficult in the program design phase based on the conventional techniques such as those described in these prior art documents.
Furthermore, it is more difficult to create, in the program test phase, test cases necessary for causing all of the possible interrupt patterns that can occur when control is passed from a higher priority interrupt process to a lower priority interrupt process.